The UnOfficial GVP-M A4060/A2060 Page


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Documentation

CN5 labeled connector on the 4060 board

According to Michael at GVP, these pins have no useful meaning for anybody but the manufacturer. They are very simply the connection to the two large Programmable Logic chips, Altera EPX880, or in older versions, EPX780. Via this connector, the Programmable Logic chips on the accelerator are being programmed "in system" after the boards were manufactured.

A4060

The following file is in Adobe Acrobat v4.0 format, of which there are a couple of .pdf file viewers available from Aminet (such as APDF). However; if you'd like a printed copy, please contact me.

Thanks to Mark Smith for contributing the Jumpers & IO Definitions section of the A4060 manual. If you have additional documentation not available here, please e-mail me.

A2060

Thanks to Michael Rozeboom for contributing the complete documentation for the GVP A2060 (available below).